CodeGen issue with HDL assemblies containing lime_spi.hdl

Description

None

Environment

'%' is not valid VHDL syntax.

See below from /hdl/platforms/matchstiq/config-matchstiq_lime_spi/gen/matchstiq_lime_spi-assy.vhd.

lime_spi_i : component lime_spi.lime_spi_defs.lime_spi_rv
port map( wci_Clk => wci_in(0).Clk,
wci_Reset_n => wci_in(0).MReset_n,
dev_out(0).rx_clk_in => lime_spi_dev%s_out(0).rx_clk_in,
dev_out(1).rx_clk_in => lime_spi_dev%s_out(1).rx_clk_in,
dev_out(0).tx_clk_in => lime_spi_dev%s_out(0).tx_clk_in,
dev_out(1).tx_clk_in => lime_spi_dev%s_out(1).tx_clk_in,
dev_out(0).rx_present => lime_spi_dev%s_out(0).rx_present,
dev_out(1).rx_present => lime_spi_dev%s_out(1).rx_present,
dev_out(0).tx_present => lime_spi_dev%s_out(0).tx_present,
dev_out(1).tx_present => lime_spi_dev%s_out(1).tx_present,
props_in => lime_spi_props%s_in,
props_out => lime_spi_props%s_out,
reset => lime_spi_reset,
sdo => lime_spi_sdo,
sclk => lime_spi_sclk,
sen => lime_spi_sen,
sdio => lime_spi_sdio,
rx_clk_in => lime_spi_rx_clk_in,
tx_clk_in => lime_spi_tx_clk_in);

Assignee

Unassigned

Reporter

Adam Ponchak

Labels

None

Components

Priority

Major
Configure