as it stands today(4/30/15) the zynq platfrom worker only works with a clock as high as 50Mhz and is built to the constrains for this. but as we bring up a new zynq based platform we just hope that one of the 4 clocks that are coming from the PS to the PL are set to 50Mhz.
To date this has been an ok solution as there has always been a 50Mhz clock but we are at the mercy of the board designer and what they set the clocks to in their boot up process. but waht if we have reasons for different control clocks for different bitstreams that are built with diffenrt constraints?
These clocks are configured by register settings on the arm that we could take control of after the board designers boot process has finished. if we wrote a utility that takes a clock number and a desired clock value this would be useful.
as far as i know we should be able to change these clocks as long as there is no bitfile loaded in the PL. Is there a way to unload a bitfile on the zynq?
This is low priority because we have a workaround on all platforms to date.
The proposed solution to this problem is to capture the clock constraints in the bitstream metadata, which is
essentially the assumptions the bitstream is making about the 4 FCLK clock generators.
Then the bitstream-loading function will program the clock generators automatically to match what the bitstream